Clock generation circuit capable of setting or controlling duty ratio of clock signal and system including clock generation circuit

ABSTRACT

A clock generation circuit receives a reference clock signal for outputting clock signals to peripheral circuits. A duty ratio of at least one of output buffer signals output from buffer circuits included in the clock generation circuit is varied so that a duty ratio of at least one of the clock signals can be varied.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a clock generation circuit and asystem including the same, and more particularly to a clock generationcircuit generating a dock signal having a duty ratio that can be set orcontrolled, and a system including the clock generation circuit.

[0003] 2. Description of the Background Art

[0004] In an LSI (Large Scale Integration) or a system using an LSI,clock signals are important signals that are required forsynchronization with internal elements, internal modules or externaldevices. Internal elements, internal modules or external devices performoperations or communications in synchronization with rising edges orfalling edges of clock signals.

[0005] In a conventional clock generation circuit generating a clocksignal, the duty ratio of the clock signal is fixed, for example, at50%.

[0006] When a workload of a circuit receiving a clock signal isdifferent between an H (logic high) level duration and an L (logic low)level duration, the operational frequency of the circuit is determinedin accordance with the period of time during which the workload isheavier, thereby decreasing the operational efficiency. Moreover, inthis case, the power consumption is abruptly increased when thefrequency of the clock signal is higher than a certain level.

[0007] In addition, when there are a plurality of circuits receivingclock signals, the current peaks occur at the same timing, resulting inincreased noises due to EMI (Electromagnetic Interference) or the like.

[0008] In order to solve the aforementioned problems, for example, aduty ratio of a clock signal may be varied. Japanese Patent Laying-OpenNos. 6-164379 and 62-42613 disclose means for varying a duty ratio of aclock signal.

[0009] The conventional clock generation circuit disclosed in JapanesePatent Laying-Open No. 6-164379 includes a phase comparator and afrequency controlled voltage generation portion receiving an output ofthe phase comparator, wherein the duty ratio of the frequency can bearbitrarily set by a capacitance charge/discharge current.

[0010] The conventional clock generation circuit disclosed in JapanesePatent Laying-Open No. 62-42613 uses a delay circuit and a logic circuitto increase or decrease a duty ratio for an input clock and to perform avariable fine adjustment of the duty ratio by changing a delay time.

[0011] The means for varying a duty ratio of a clock signal, however, isnot limited to the means disclosed in the prior art references above.Desirably, the duty ratio of the clock signal can be set flexibly inaccordance with the scale or characteristics of the circuit receivingthe clock signal.

SUMMARY OF THE INVENTION

[0012] An object of the present invention is to provide a clockgeneration circuit capable of setting or controlling a duty ratio of aclock signal flexibly in accordance with a scale or characteristic of acircuit receiving a clock signal, and a system including the same.

[0013] A clock generation circuit in accordance with an aspect of thepresent invention includes: a frequency-multiplying circuit receiving aninput of a reference clock signal and outputting a same orfrequency-multiplied clock signal of the reference clock signal; and abuffering portion buffering the clock signal. The buffering portionincludes at least one buffer circuit buffering the clock signal suchthat a logic low period and a logic high period of the clock signal aredifferent from each other.

[0014] A clock generation circuit in accordance with another aspect ofthe present invention includes: a frequency-multiplying circuitreceiving an input of a reference clock signal and outputting a same orfrequency-multiplied clock signal of the reference clock signal, havinga logic high period and a logic low period different from each other;and a buffering portion buffering the clock signal.

[0015] A clock generation circuit in accordance with yet another aspectof the present invention includes: a frequency-multiplying circuitreceiving an input of a reference clock signal and outputting a same orfrequency-multiplied clock signal of the reference clock signal; awaveform generation circuit outputting a duty ratio control signal; andan AND gate receiving the clock signal and the duty ratio controlsignal. In the duty ratio control signal, a period of time during whichboth of the clock signal and the duty ratio control signal are logichigh is different from the other period of time.

[0016] A clock generation circuit in accordance with still anotheraspect of the present invention includes: a frequency-multiplyingcircuit receiving an input of a reference clock signal and outputting asame or frequency-multiplied clock signal of the reference clock signal;a waveform generation circuit outputting a duty ratio control signal;and an OR gate receiving the clock signal and the duty ratio controlsignal. In the duty ratio control signal, a period of time during whichboth of the clock signal and the duty ratio control signal are logic lowis different from the other period of time.

[0017] A clock generation circuit in accordance with a further aspect ofthe present invention includes: a frequency-multiplying circuitreceiving an input of a reference clock signal and outputting a same orfrequency-multiplied clock signal of the reference clock signal; and abuffering portion buffering the clock signal. The buffering portionincludes at least one buffer circuit capable of changing a duty ratio ofthe clock signal.

[0018] A clock generation circuit in accordance with a still furtheraspect of the present invention includes: a frequency-multiplyingcircuit receiving an input of a reference clock signal and outputting asame or frequency-multiplied clock signal of the reference clock signal;and a buffering portion buffering the clock signal. Thefrequency-multiplying circuit can change a duty ratio of the clocksignal.

[0019] A clock generation circuit in accordance with a still furtheraspect of the present invention includes: a frequency-multiplyingcircuit receiving an input of a reference clock signal and outputting asame or frequency-multiplied clock signal of the reference clock signal;a waveform generation circuit generating a duty ratio control signal;and an AND gate receiving the clock signal and the duty ratio controlsignal. In the duty ratio control signal, a ratio between a period oftime during which both of the clock signal and the duty ratio controlsignal are logic high and the other period of time can be varied.

[0020] A clock generation circuit in accordance with a further aspect ofthe present invention includes: a frequency-multiplying circuitreceiving an input of a reference clock signal and outputting a same orfrequency-multiplied clock signal of the reference clock signal; awaveform generation circuit generating a duty ratio control signal; andan OR gate receiving the clock signal and the duty ratio control signal.In the duty ratio control signal, a ratio between a period of timeduring which both of the clock signal and the duty ratio control signalare logic low and the other period of time can be varied.

[0021] A system in accordance with an aspect of the present inventionincludes: a clock generation circuit outputting a clock signal; a clockcontrolling circuit controlling a duty ratio of the clock signal using acontrol signal; and a central processing unit controlling the clockcontrolling circuit. The clock generation circuit includes afrequency-multiplying circuit receiving an input of a reference clocksignal and outputting the clock signal same as or multiplied infrequency of the reference clock signal, and a buffering portionbuffering the clock signal. The buffering portion includes at least onebuffer circuit capable of changing a duty ratio of the clock signal.

[0022] A system in accordance with another aspect of the presentinvention includes: a clock generation circuit outputting a clocksignal; a clock controlling circuit controlling a duty ratio of theclock signal using a control signal; and a central processing unitcontrolling the clock controlling circuit. The clock generation circuitincludes a frequency-multiplying circuit receiving an input of areference clock signal and outputting the clock signal same as ormultiplied in frequency of the reference clock signal, and a bufferingportion buffering the clock signal. The frequency-multiplying circuitcan change a duty ratio of the clock signal.

[0023] A system in accordance with yet another aspect of the presentinvention includes: a clock generation circuit outputting a clocksignal; a clock controlling circuit controlling a duty ratio of theclock signal using a control signal; and a central processing unitcontrolling the clock controlling circuit. The clock generation circuitincludes a frequency-multiplying circuit receiving an input of areference clock signal and outputting the clock signal same as ormultiplied in frequency of the reference clock signal, a waveformgeneration circuit generating a duty ratio control signal, and an ANDgate receiving the dock signal and the duty ratio control signal. In theduty ratio control signal, a ratio between a period of time during whichboth of the clock signal and the duty ratio control signal are logichigh and the other period of time can be varied.

[0024] A system in accordance with a further aspect of the presentinvention includes: a clock generation circuit outputting a clocksignal; a clock controlling circuit controlling a duty ratio of theclock signal using a control signal; and a central processing unitcontrolling the clock controlling circuit. The clock generation circuitincludes a frequency-multiplying circuit receiving an input of areference clock signal and outputting the clock signal same as ormultiplied in frequency of the reference clock signal, a waveformgeneration circuit generating a duty ratio control signal, and an ORgate receiving the clock signal and the duty ratio control signal. Inthe duty ratio control signal, a ratio between a period of time duringwhich both of the clock signal and the duty ratio control signal arelogic low and the other period of time can be varied.

[0025] As described above, in accordance with the present invention, aduty ratio of a clock signal can be set or controlled flexibly dependingon a scale or characteristic of a circuit receiving the clock signal.

[0026] The foregoing and other objects, features, aspects and advantagesof the present invention will become more apparent from the followingdetailed description of the present invention when taken in conjunctionwith the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0027]FIG. 1 is a block diagram showing a clock generation circuit 1Aand a peripheral circuit thereof in accordance with a first embodimentof the present invention.

[0028]FIG. 2 is a circuit diagram showing a circuit configuration of abuffer circuit 10 a in accordance with the first embodiment of thepresent invention.

[0029]FIG. 3 is an operational waveform diagram illustrating a circuitoperation of buffer circuit 10 a in accordance with the first embodimentof the present invention.

[0030]FIG. 4 is a circuit diagram showing a circuit configuration of abuffer circuit 10 b in accordance with the first embodiment of thepresent invention.

[0031]FIG. 5 is an operational waveform diagram illustrating a circuitoperation of buffer circuit 10 b in accordance with the first embodimentof the present invention.

[0032]FIG. 6 is a circuit diagram showing a circuit configuration of abuffer circuit 10 c in accordance with the first embodiment of thepresent invention.

[0033]FIG. 7 is a circuit diagram showing a circuit configuration of abuffer circuit 10 d in accordance with the first embodiment of thepresent invention.

[0034]FIG. 8 is an operational waveform diagram illustrating a circuitoperation of buffer circuit 10 d in accordance with the first embodimentof the present invention.

[0035]FIG. 9 is a circuit diagram showing a circuit configuration of abuffer circuit 10 e in accordance with the first embodiment of thepresent invention.

[0036]FIG. 10 is a circuit diagram showing a circuit configuration of abuffer circuit 10 f in accordance with the first embodiment of thepresent invention.

[0037]FIG. 11 is an operational waveform diagram illustrating a circuitoperation of buffer circuit 10 f in accordance with the first embodimentof the present invention.

[0038]FIG. 12 is a circuit diagram showing a circuit configuration of abuffer circuit 10 g in accordance with the first embodiment of thepresent invention.

[0039]FIG. 13 is an operational waveform diagram illustrating a circuitoperation of buffer circuit 10 g in accordance with the first embodimentof the present invention.

[0040]FIG. 14 is a block diagram showing a clock generation circuit 1Band a peripheral circuit thereof in accordance with the first embodimentof the present invention.

[0041]FIG. 15 is a circuit diagram showing a circuit configuration of aPLL circuit 2 a in accordance with a second embodiment of the presentinvention.

[0042]FIG. 16 is an operational waveform diagram illustrating a circuitoperation of PLL circuit 2 a in accordance with the second embodiment ofthe present invention.

[0043]FIG. 17 is a circuit diagram showing a circuit configuration of aPLL circuit 2 b in accordance with the second embodiment of the presentinvention.

[0044]FIG. 18 is an operational waveform diagram illustrating a circuitoperation of PLL circuit 2 b in accordance with the second embodiment ofthe present invention.

[0045]FIG. 19 is a circuit diagram showing a circuit configuration of aclock generation circuit 1C in accordance with a third embodiment of thepresent invention.

[0046]FIG. 20 is an operational waveform diagram illustrating a circuitoperation of clock generation circuit 1C in accordance with the thirdembodiment of the present invention.

[0047]FIG. 21 is a circuit diagram showing a circuit configuration of aclock generation circuit 1D in accordance with the third embodiment ofthe present invention.

[0048]FIG. 22 is an operational waveform diagram illustrating a circuitoperation of clock generation circuit 1D in accordance with the thirdembodiment of the present invention.

[0049]FIG. 23 is a block diagram showing a configuration of a system 100in accordance with a fourth embodiment of the present invention.

[0050]FIG. 24 is a block diagram showing a configuration of a system 200in accordance with the fourth embodiment of the present invention.

[0051]FIG. 25 is a block diagram showing a configuration of a system 300in accordance with the fourth embodiment of the present invention.

[0052]FIG. 26 is a block diagram showing a configuration of a system 400in accordance with the fourth embodiment of the present invention.

[0053]FIG. 27 is a block diagram showing a configuration of a system 500in accordance with the fourth embodiment of the present invention.

[0054]FIG. 28 is a block diagram showing a configuration of a system 600in accordance with the fourth embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0055] In the following, the embodiments of the present invention willbe described in detail with reference to the figures. It is noted thatin the figures, the same or corresponding parts will be denoted with thesame reference characters, and the description thereof will not berepeated.

[0056] [First Embodiment]

[0057]FIG. 1 is a block diagram showing a clock generation circuit 1Aand peripheral circuits thereof in accordance with a first embodiment ofthe present invention.

[0058] Clock generation circuit 1A of the first embodiment shown in FIG.1 receives a reference clock signal CLK0 to output clock signals CLK1,CLK2, and CLK3 to peripheral circuits 1000, 2000, and 3000,respectively. Here, peripheral circuits 1000, 2000, and 3000 may be arandom logic circuit, an operation circuit, a register circuit, a memorycircuit, an analog circuit, or the like.

[0059] Clock generation circuit 1A includes a PLL (Phase Locked Loop) 2,and buffer circuits 10-0A, 10-1A, 10-2A, and 10-3A. PLL circuit 2receives a reference clock signal CLK0. Buffer circuit 10-0A receivesthe output from PLL circuit 2. Buffer circuits 10-1A, 10-2A, 10-3Areceive the output of buffer circuit 10-0A to output clock signals CLK1,CLK2, CLK3, respectively.

[0060] Clock generation circuit 1A in accordance with the firstembodiment is configured to vary the duty ratio of at least one ofoutput buffer signals output from buffer circuits 10-0A, 10-1A, 10-2A,10-3A so as to vary the duty ratio of the clock signal output from clockgeneration circuit 1A flexibly.

[0061] In the following, exemplary buffer circuit configurations of thefirst embodiment for forming at least one of buffer circuits 10-0A,10-1A, 10-2A, 10-3A will be described.

[0062]FIG. 2 is a circuit diagram showing a circuit configuration of abuffer circuit 10 a in accordance with the first embodiment of thepresent invention.

[0063] Buffer circuit 10 a of the first embodiment shown in FIG. 2 isformed of inverters 11, 14 of two stages connected in series. Inverter11 receives an input buffer signal BIN. Inverter 14 receives the outputfrom inverter 11 and outputs an output buffer signal BOUT.

[0064] Inverter 11 includes a P-channel MOS transistor 12 and anN-channel MOS transistor 13 connected in series between a power supplynode and a ground node. The gates of P-channel MOS transistor 12 andN-channel MOS transistor 13 receive input buffer signal BIN. The drainsof P-channel MOS transistor 12 and N-channel MOS transistor 13 areconnected to the input terminal of inverter 14.

[0065] In buffer circuit 10 a of the first embodiment shown in FIG. 2,the gate delay amount for the input signal at N-channel MOS transistor13 is larger than the gate delay amount for the input signal atP-channel MOS transistor 12. The degree of the gate delay amount dependsgreatly on the difference in the source-drain current of the MOStransistor.

[0066]FIG. 3 is an operational waveform diagram illustrating a circuitoperation of buffer circuit 10 a in accordance with the first embodimentof the present invention.

[0067] Since the gate delay amount for the input signal at N-channel MOStransistor 13 is larger than the gate delay amount for the input signalat P-channel MOS transistor 12, the delay amount of input buffer signalBIN at inverter 11 is larger during the transition from H level to Llevel than during the transition from L level to H level.

[0068] Thus, where the duty ratio of input buffer signal BIN is 50%,output buffer signal BOUT has an H level period TH longer than an Llevel period TL, as shown in FIG. 3. In the following, it is assumedthat the duty ratio of input buffer signal BIN is 50%, unless otherwisespecified. In addition, a large/small gate delay amount for an inputsignal at a transistor is also referred to as a large/small drivingcapability of a transistor.

[0069] In buffer circuit 10 a of the first embodiment, although the gatedelay amount for the input signal at N-channel MOS transistor 13 islarger, the gate delay amount for the input signal at P-channel MOStransistor 12 may be larger, on the contrary. In this case, outputbuffer signal BOUT has a longer L level, which is effective for acircuit or a system having a larger amount of operations in the L levelperiod.

[0070] In buffer circuit 10 a of the first embodiment, although the gatedelay amount for the input signal is different between P-channel MOStransistor 12 and N-channel MOS transistor 13 which are included in theformer stage, this may be applied to inverter 14 on the latter stage. Inthis case, the similar effect can be obtained.

[0071] As described above, buffer circuit 10 a of the first embodimentuses such transistors different in driving capability to vary the dutyratio of the output buffer signal. Therefore, after manufacturing, itbecomes difficult to change the duty ratio of the output buffer signal.The buffer circuit that can eliminate such a problem will now bedescribed. In the following, it is assumed that the driving capabilityis equal among all the transistors included in the circuit, unlessotherwise specified.

[0072]FIG. 4 is a circuit diagram showing a circuit configuration of abuffer circuit 10 b in accordance with the first embodiment of thepresent invention.

[0073] Buffer circuit 10 b of the first embodiment as shown in FIG. 4 isformed of inverters 21 and 29 of two stages connected in series.Inverter 21 includes a P-channel MOS transistor 22 and an N-channel MOStransistor 23 connected in series between a power supply node and aground node, and a driving capability control circuit 24.

[0074] The gates of P-channel MOS transistor 22 and N-channel MOStransistor 23 receive input buffer signal BIN. Inverter 29 receives theinput from an output node Nb and outputs output buffer signal BOUT.

[0075] Driving capability control circuit 24 includes an OR gate 25having one input inverted, an AND gate 26, and a P-channel MOStransistor 27 and an N-channel MOS transistor 28 connected in seriesbetween the power supply node and the ground node. P-channel MOStransistors 22, 27 are connected in parallel between the power supplynode and output node Nb. N-channel MOS transistors 23, 28 are connectedin series between output node Nb and the ground node.

[0076] OR gate 25 receives input buffer signal BIN and an inverted,driving capability control signal DRVP and has its output connected tothe gate of P-channel MOS transistor 27. AND gate 26 receives inputbuffer signal BIN and a driving capability control signal DRVN and hasits output connected to the gate of N-channel MOS transistor 28.

[0077]FIG. 5 is an operational waveform diagram illustrating a circuitconfiguration of buffer circuit 10 b in accordance with the firstembodiment of the present invention.

[0078] When driving capability control signals DRVP and DRVN both are atL level (prior to time t1), logical gate 25 and AND gate 26 in drivingcapability control circuit 24 output H level and L level, respectively.As a result, P-channel MOS transistor 27 and N-channel MOS transistor 28both turn off.

[0079] Therefore, in buffer circuit 10 b, the driving capability on theside of P-channel MOS transistors 22, 27 becomes equal to that on theside of N-channel MOS transistors 23, 28, prior to time t1. Input buffersignal BIN is thus output as output buffer signal BOUT after beingdelayed as it is for a certain time period, prior to time t1, as shownin FIG. 5.

[0080] When driving capability control signals DRVP, DRVN are at Hlevel, L level, respectively (times t1-t2), the output of logical gate25 is correlated with the change of input buffer signal BIN, whereas theoutput of AND gate 26 is always at L level. As a result, P-channel MOStransistors 22, 27 both turn on when input buffer signal BIN is at Llevel, whereas only N-channel MOS transistor 23 turns on and N-channelMOS transistor remains off when input buffer signal BIN is at H level.

[0081] Therefore, at times t1-t2, in buffer circuit 10 b, the drivingcapability in inverter 21 is greater on the side of P-channel MOStransistors 22, 27 than the driving capability on the side of N-channelMOS transistors 23, 28. In other words, the delay amount of input buffersignal BIN at inverter 21 is larger during the transition from L levelto H level than during the transition from H level to L level.Therefore, output buffer signal BOUT has an L level period TL1 longerthan an H level period TH1 at times t1-t2, as shown in FIG. 5.

[0082] When driving capability control signals DRVP, DRVN are at Llevel, H level, respectively (after time t2), the output of logical gate25 is always at H level, whereas the output of AND gate 26 is correlatedwith the change of input buffer signal BIN. As a result, only P-channelMOS transistor 22 turns on and P-channel MOS transistor 27 remains offwhen input buffer signal BIN is at L level, whereas N-channel MOStransistors 23, 28 both turn on when input buffer signal BIN is at Hlevel.

[0083] Therefore, after time t2, in buffer circuit 10 b, the drivingcapability in inverter 21 is greater on the side of the N-channel MOStransistors 23, 28 than on the side of P-channel MOS transistors 22, 27.In other words, the delay amount of input buffer signal BIN at inverter21 is greater during the transition from H level to L level than duringthe transition from L level to H level. Therefore, output buffer signalBOUT has an H level period TH2 longer than an L level period TL2, aftertime t2, as shown in FIG. 5.

[0084] In this way, in buffer circuit 10 b of the first embodiment, theduty ratio of output buffer signal BOUT can be adjusted by providingdriving capability control circuit 25 in inverter 21 and controlling thedriving capabilities on the P-channel MOS transistor side and on theN-channel MOS transistor side using driving capability control signalsDRVP, DRVN.

[0085]FIG. 6 is a circuit diagram showing a circuit configuration of abuffer circuit 10 c in accordance with the first embodiment of thepresent invention.

[0086] Buffer circuit 10 c shown in FIG. 6 is formed of an inverter 31,which is a replacement of inverter 21 in buffer circuit 10 b shown inFIG. 4. Inverter 31 differs from inverter 21 in that driving capabilitycontrol circuit 24 is provided in multiple stages of driving capabilitycontrol circuits 24.1, 24.2 . . . etc. Such provision of multiple stagesof driving capability control circuit 24 allows a finer adjustment of aduty ratio of output buffer signal BOUT.

[0087] Although buffer circuits 10 a-10 c illustrated in FIGS. 2-6utilize the difference in the driving capability of transistors tocontrol the duty ratio, the signal delay between inverters may be usedto control the duty ratio. Such an embodiment will now be described.

[0088]FIG. 7 is a circuit diagram showing a circuit configuration of abuffer circuit 10 d in accordance with the first embodiment of thepresent invention.

[0089] Buffer circuit 10 d of the first embodiment shown in FIG. 7includes an inverter 41, a timing control circuit 44, and an inverter49.

[0090] Inverter 41 has a P-channel MOS transistor 42 and an N-channelMOS transistor 43 connected in series between a power supply node and aground node. The gates of P-channel MOS transistor 42 and N-channel MOStransistor 43 receive input buffer signal BIN.

[0091] Timing control circuit 44 has an NAND gate 45, an AND gate 46,and a P-channel MOS transistor 47 and an N-channel MOS transistor 48connected in series between the power supply node and the ground node.NAND gate 45 receives a timing control signal TMGP and input buffersignal BIN and has the output connected to the gate of P-channel MOStransistor 47. AND gate 46 receives a timing control signal TMGN andinput buffer signal BIN and has the output connected to the gate ofN-channel MOS transistor 48.

[0092] Inverter 49 receives the inputs from the drains of P-channel MOStransistors 42, 47 and N-channel MOS transistors 43, 48 and outputsoutput buffer signal BOUT.

[0093]FIG. 8 is an operational waveform diagram illustrating a circuitoperation of buffer circuit 10 d in accordance with the first embodimentof the present invention.

[0094] When timing control signals TMGP, TMGN both are at L level (priorto time t1), NAND gate 45 and AND gate 46 within timing control circuit44 output H level and L level, respectively. As a result, P-channel MOStransistor 47 and N-channel MOS transistor 48 both turn off.

[0095] Buffer circuit 10 d is thus equivalent to inverter 41 andinverter 49 as serially connected. Therefore, input buffer signal BIN isoutput as output buffer signal BOUT as being delayed as it is for acertain time period, prior to time t1, as shown in FIG. 8.

[0096] When timing control signals TMGP and TMGN are at H level and Llevel, respectively (times t1-t2), respectively, NAND gate 45 outputs Llevel and H level at the time of H level and L level of input buffersignal BIN, respectively, and AND gate 46 always outputs L level, withintiming control circuit 44.

[0097] Therefore, when input buffer signal BIN goes to H level, an Llevel signal is output from inverter 41 to inverter 49, and outputbuffer signal BOUT initially goes to H level. However, output buffersignal BOUT soon goes to L level, because P-channel MOS transistor 47 intiming control circuit 44 thereafter turns on to provide a power supplypotential VCC (H level) to the input of inverter 49.

[0098] Thus, when timing control signals TMGP and TMGN are at H leveland L level, respectively (times t1-t2), output buffer signal BOUT hasan L level period TL1 longer than an H level period TH1, as shown inFIG. 8.

[0099] When timing control signals TMGP and TMGN are at L level and Hlevel, respectively (after time t2), in timing control circuit 44, NANDgate 45 always outputs H level and AND gate 46 outputs H level and Llevel at the time of H level and L level of input buffer signal BIN,respectively.

[0100] Therefore, when input buffer signal BIN goes to H level, an Llevel signal is output from inverter 41 to inverter 49, and outputbuffer signal BOUT goes to H level. In addition, N-channel MOStransistor 48 in timing control circuit 44 turns on to provide groundpotential GND (L level) to the input of inverter 49. When input buffersignal BIN thereafter goes to L level, an H level signal is output frominverter 41 to inverter 49. As N-channel MOS transistor 48 remains offfor a while, ground potential GND (L level) is continuously supplied tothe input of inverter 49 for a while, and output buffer signal BOUTremains at H level for a while.

[0101] Thus, when timing control signals TMGP and TMGN are at L leveland H level, respectively (after time t2), output buffer signal BOUT hasan H level period TH2 longer than an L level period TL2, as shown inFIG. 8.

[0102] In this way, in buffer circuit 10 d of the first embodiment, theduty ratio of output buffer signal BOUT can be adjusted by insertingtiming control circuit 44 between inverter 41 and inverter 49 andcontrolling a signal delay between the inverters using timing controlsignals TMGP, TMGN.

[0103]FIG. 9 is a circuit diagram showing a circuit configuration of abuffer circuit 10 e in accordance with the first embodiment of thepresent invention.

[0104] Buffer circuit 10 e of the first embodiment shown in FIG. 9 isconfigured such that timing control circuit 44 in buffer circuit 10 dshown in FIG. 7 is divided in multiple stages of timing control circuits44.1, 44.2, . . . etc. Such provision of multiple stages of timingcontrol circuit 44 allows a finer adjustment of a duty ratio of outputbuffer signal BOUT.

[0105]FIG. 10 is a circuit diagram showing a circuit configuration of abuffer circuit 10 f in accordance with the first embodiment of thepresent invention.

[0106] Buffer circuit 10 f of the first embodiment shown in FIG. 10includes a delay circuit 51 and an AND gate 52. Delay circuit 51 cancontrol a delay time in accordance with a delay control signal DLY. ANDgate 52 receives input buffer signal BIN delayed by delay circuit 51 andinput buffer signal BIN not delayed by delay circuit 51, and outputsoutput buffer signal BOUT.

[0107]FIG. 11 is an operational waveform diagram illustrating a circuitoperation of buffer circuit 10 f in accordance with the first embodimentof the present invention. Here, for the sake of brevity, descriptionwill be made to a case where delay control signal DLY varies in twolevels of H level and L level. This, however, will be described by wayof example, and delay control signal DLY can generally be varied inmulti-levels or continuously.

[0108] When delay control signal DLY is at L level (prior to time t1),delay circuit 51 delays the input signal by a prescribed delay timeDLY1. When input buffer signal BIN changes from H level to L level, ANDgate 52 has its output changed from H level to L level immediately afterreceiving input buffer signal BIN not delayed by delay circuit 51. Onthe other hand, when input buffer signal BIN changes from L level to Hlevel, AND gate 52 has its output unchanged from L level to H leveluntil receiving input buffer signal BIN delayed by delay circuit 51 bydelay time DLY1. Therefore, output buffer signal BOUT has an L levelperiod TL1 longer than an H level period TH, prior to time t1, as shownin FIG. 11.

[0109] When delay control signal DLY is at H level (after time t1),delay circuit 51 delays the input signal by a prescribed delay timeDLY2. Therefore, output buffer signal BOUT has an L level period TL2longer than an H level period TH, after time T1, as shown in FIG. 11.Since it is assumed that delay time DLY2 is longer than delay time DLY1,the L level period TL2 after time t1 is longer than the L level periodTL1 before time t1.

[0110] In this way, in buffer circuit 10 f of the first embodiment, theduty ratio of output buffer signal BOUT can be varied in accordance withthe delay control signal by providing a delay circuit having a delaytime length that can be controlled by a delay control signal, prior toone input of the AND gate.

[0111]FIG. 12 is a circuit diagram showing a circuit configuration of abuffer circuit 10 g in accordance with a first embodiment of the presentinvention.

[0112] Buffer circuit 10 g of the first embodiment shown in FIG. 12includes a delay circuit 51 and an OR gate 53. Delay circuit 51 cancontrol a delay time in accordance with delay control signal DLY. ORgate 53 receives input buffer signal BIN delayed by delay circuit 51 andinput buffer signal BIN not delayed by delay circuit 51, and outputsoutput buffer signal BOUT.

[0113]FIG. 13 is an operational waveform diagram illustrating a circuitoperation of buffer circuit 10 g in accordance with the first embodimentof the present invention. Here, for the sake of brevity, descriptionwill be made to a case where delay control signal DLY changes in twolevels of H level and L level. This, however, will be described only byway of example, and delay control signal DLY can generally be changed inmulti-levels or continuously.

[0114] When delay control signal DLY is at L level (prior to time t1),delay circuit 51 delays an input signal by a prescribed delay time DLY1.When input buffer signal BIN changes from L level to H level, OR gate 53has its output changed from L level to H level immediately afterreceiving input buffer signal BIN not delayed by delay circuit 51. Onthe other hand, when input buffer signal BIN changes from H level to Llevel, OR gate 53 has its output unchanged from H level to L level untilreceiving input buffer signal BIN delayed by delay time DLY1 by delaycircuit 51. Therefore, output buffer signal BOUT has an H level periodTH1 longer than an L level period TL, prior to time t1, as shown in FIG.13.

[0115] When delay control signal DLY is at H level (after time t1),delay circuit 51 delays an input signal by a prescribed delay time DLY2.Therefore, output buffer signal BOUT has an H level period TH2 longerthan an L level period TL, after time t1, as shown in FIG. 13.Furthermore, the H level period TH2 after time t1 is longer than the Hlevel period TH1 before time t1, since it is assumed that delay timeDLY2 is longer than delay time DLY1.

[0116] In this way, in buffer circuit 10 g of the first embodiment, theduty ratio of output buffer signal BOUT can be varied in accordance withthe delay control signal by providing a delay circuit having a delaytime length that can be controlled by a delay control signal, prior toone input of the OR gate.

[0117] In the following, how buffer circuits 10 a-10 g of the firstembodiment as described above are adapted to buffer circuits 10-0A,10-1A, 10-2A, 10-3A in clock generation circuit 1A in FIG. 1 will bedescribed based on specific examples.

[0118] When the amount of operations during the H level period is largein all of peripheral circuits 1000-3000 receiving clock signalsCLK1-CLK3, respectively, for example, the H level period in all of clocksignals CLK1-CLK3 can be lengthened by adapting buffer circuits 10 a-10g in the first embodiment to buffer 10-0A. Thus, increased speed andreduced power consumption in peripheral circuits 1000-3000 can berealized.

[0119] When the amount of operations during the H level period is largeonly in peripheral circuit 1000 receiving clock signal CLK1, forexample, the H level period of dock signal CLK1 can be lengthened onlyin peripheral circuit 1000 having a large amount of operations in the Hlevel period, by adapting buffer circuits 10 a-10 g in the firstembodiment to buffer 10-1A. As a result, peripheral circuits 1000-3000as a whole can efficiently be increased in speed and reduced in powerconsumption.

[0120] In this case, since clock signal CLK1 has the falling edgeshifted from those of clock signals CLK2, CLK3, peripheral circuit 1000operating at the falling edge has operation timing also shifted fromthose of peripheral circuits 2000, 3000. Therefore, the timings ofcurrent peak are also shifted in peripheral circuits 1000-3000.Therefore, where clock generation circuit 1A is incorporated into anLSI, for example, the malfunction of LSI due to excess current is lesslikely to occur and the noise due to EMI can also be reduced.

[0121] As described above, the duty ratio of clock signals CLK1, CLK2,CLK3 may be set for all of peripheral circuits 1000-3000 or for aspecific one of peripheral circuits 1000-3000. The duty ratio of theclock signal can be set flexibly depending on the system in this manner,so that it is possible to construct a system achieving highestperformance for each module.

[0122] With reference to FIG. 1, as an example of clock generationcircuit 1A in accordance with the first embodiment of the presentinvention, power supply potential VCC or ground potential GND may bechanged only in at least one of buffer circuits 10-0A, 10-1A, 10-2A,10-3A. In this case, as the logical threshold value of the buffercircuit is shifted, the duty ratio of the output buffer signal can bechanged. It is noted that the duty ratio of the output buffer signal canbe adjusted using a control signal by adjusting the amount of change inpower supply potential VCC or ground potential GND using the controlsignal.

[0123] With reference to FIG. 1, as another example of clock generationcircuit 1A in accordance with the first embodiment of the presentinvention, a substrate potential of a transistor included in the buffercircuit may be changed only in at least one of buffer circuits 10-0A,10-1A, 10-2A, 10-3A. In this case, as the logical threshold value of thebuffer circuit is shifted, the duty ratio of the output buffer signalcan be changed. It is noted that the duty ratio of the output buffersignal can be adjusted using a control signal by adjusting the amount ofchange in substrate potential of the transistor using the controlsignal.

[0124] As described above, in accordance with the first embodiment,increased speed and reduced power consumption of the system includingclock generation circuit 1A can be realized by varying the duty ratio ofat least one of the output buffer signals output from buffer circuits10-0A, 10-1A, 10-2A, 10-3A that are components of clock generationcircuit 1A.

[0125] [Second Embodiment]

[0126]FIG. 14 is a block diagram showing a clock generation circuit 1Band peripheral circuits thereof in accordance with a second embodimentof the present invention.

[0127] Clock generation circuit 1B of the second embodiment shown inFIG. 14 receives reference clock signal CLK0 to output clock signalsCLK1, CLK2, CLK3 to peripheral circuits 1000, 2000, 3000, respectively.Here, peripheral circuits 1000, 2000, 3000 may be, for example, a randomlogic circuit, an operation circuit, a register circuit, a memorycircuit, an analog circuit, or the like.

[0128] Clock generation circuit 1B includes a PLL circuit 2B, and buffercircuits 10-0, 10-1, 10-2, 10-3. PLL circuit 2B receives reference clocksignal CLK0. Buffer circuit 10-0 receives the output from PLL circuit2B. Buffer circuits 10-1, 10-2, 10-3 receive the output from buffercircuit 10-0 to output clock signals CLK1, CLK2, CLK3, respectively.

[0129] Clock generation circuit 1B of the second embodiment isconfigured to vary the duty ratio of the output PLL signal output fromPLL circuit 2B so as to vary the duty ratio of the clock signal outputfrom clock generation circuit 1B.

[0130] In the following, exemplary configurations of the PLL circuit ofthe second embodiment for forming PLL circuit 2B will be described.

[0131]FIG. 15 is a circuit diagram showing a PLL circuit 2 a inaccordance with the second embodiment of the present invention.

[0132] PLL circuit 2 a of the second embodiment shown in FIG. 15 is adigital PLL circuit, including a comparator 61, a control circuit 62, acounter 63, a delay line 64, and an AND gate 65. The output signal fromdelay line 64 is inverted and input to one input terminal of AND gate65.

[0133] Delay line 64 and AND gate 65 constitute a ring oscillator 66.Ring oscillator 66 oscillates so that an output PLL signal POUT isoutput from AND gate 65. Output PLL signal POUT is fed back to delayline 64 and is also input to comparator 61 and control circuit 62.

[0134] Comparator 61 compares output PLL signal POUT with referenceclock signal CLK0 in phase and outputs the phase comparison result tocounter 63.

[0135] Control circuit 62 increments/decrements a digital count valueCNT output from counter 63 when a count value control signal PCNT isactivated. Control circuit 62 also outputs an enable signal EN forcontrolling the oscillation of ring oscillator 66 to the other inputterminal of AND gate 65.

[0136] Counter 63 determines digital count value CNT based on the phasecomparison result output from comparator 61. Digital count value CNT isincremented/decremented in accordance with an instruction toincrement/decrement a digital count value CNT, which is output fromcontrol circuit 62 when count value control signal PCNT is activated.

[0137] Delay line 64 receives digital count value CNT output fromcounter 63 to adjust a delay time. Varied delay time at delay line 64allows the duty ratio of output PLL signal POUT output from AND gate 65to be varied. Output PLL signal POUT has the same or multipliedfrequency of reference clock signal CLK0.

[0138]FIG. 16 is an operational waveform diagram illustrating a circuitoperation of PLL circuit 2 a in accordance with the second embodiment ofthe present invention.

[0139] When count value control signal is at L level (prior to time t1),control circuit 62 does not output the instruction toincrement/decrement digital count value CNT, so that the oscillationstate of ring oscillator 66 is stable and digital count value CNT takesa constant value n. At this time, the duty ratio of output PLL signal is50%.

[0140] When count value control signal PCNT is at H level (after timet1), control circuit 62 outputs the instruction to increment/decrementdigital count value CNT, and digital count value CNT switches to n+1 atthe time of rising and to n+1 at the time of failing of output PLLsignal POUT. As a result, the delay time of delay line 64 is long whenoutput PLL signal POUT is at H level, and it is short when POUT is at Llevel.

[0141] Therefore, when count value control signal PCNT is at H level, asshown in FIG. 16, output PLL signal POUT has a longer H level periodthan an L level period and has the duty ratio changed from 50%. In thismanner, in PLL circuit 2 a of the second embodiment, the duty ratio ofoutput PLL signal POUT can be adjusted by operating theactivation/inactivation of count value control signal PCNT.

[0142] In PLL circuit 2 a of the second embodiment, digital count valueCNT is switched between n+1 and n−1 in accordance with the rising andfalling of output PLL signal POUT, though the present invention is notlimited thereto. Generally, it can be switched between n+p and n−p(where p is a natural number).

[0143] Although the duty ratio of output PLL signal POUT has beendescribed above as being controlled by activation/inactivation of countvalue control signal PCNT, the duty ratio of output PLL signal POUT maynot always be controllable. For example, a constant ratio between the Hlevel period and the L level period of output PLL signal POUT can alwaysbe kept by fixing count value control signal PCNT at H level. Here, theratio between the H level period and the L level period of output PLLsignal POUT is stable because the activation/inactivation of count valuecontrol signal PCNT is not used.

[0144]FIG. 17 is a circuit diagram showing a circuit configuration of aPLL circuit 2 b in accordance with the second embodiment of the presentinvention.

[0145] PLL circuit 2 b of the second embodiment shown in FIG. 17 is adigital PLL circuit, including a comparator 71, a control circuit 72, acounter 73, delay lines 74, 75, an NAND gate 76, a selector 77, and anAND gate 78. It is noted that the output signal of selector 77 isinverted and input to one input terminal of AND gate 78.

[0146] Delay lines 74, 75, selector 77, and AND gate 78 constitute aring oscillator 79. Ring oscillator 79 oscillates so that output PLLsignal POUT is output from AND gate 78. Output PLL signal POUT is fedback to delay line 74 and is also output to one input terminal of NANDgate 76 and comparator 71.

[0147] Comparator 71 compares output PLL signal POUT with referenceclock signal CLK0 in phase and outputs the phase comparison result tocounter 73. Control circuit 72 outputs enable signal EN for controllingthe oscillation of ring oscillator 79 to the other input terminal of ANDgate 78. Counter 73 determines digital count value CNT based on thephase comparison result output from comparator 71.

[0148] Delay lines 74, 75 receive digital count value CNT output fromcounter 73 to determine a delay time. The output signal output fromdelay line 74 is input to delay line 75 and is also input to an inputterminal B of selector 77. The output signal output from delay line 75is input to an input terminal A of selector 77.

[0149] NAND gate 76 receives a selector control signal PSEL and anoutput PLL signal POUT to output a select signal SEL to selector 77.Selector 77 receives a signal from input terminal A at the time of Llevel of select signal SEL and a signal from input terminal B at thetime of H level of select signal SEL, and inverts the signal for inputto one input of AND gate 78.

[0150]FIG. 18 is an operational waveform diagram illustrating a circuitoperation of PLL circuit 2 b in accordance with the second embodiment ofthe present invention.

[0151] When selector control signal SEL is at L level (prior to timet1), select signal SEL is always at H level, irrespective of the stateof output PLL signal POUT. Therefore, selector 77 always selects inputterminal B without passing through delay line 75. Therefore, ringoscillator 79 is stable and the duty ratio of output PLL signal POUT is50%.

[0152] When selector control signal PSEL is at H level (after time t1),select signal SEL is an inversion signal of output PLL signal POUT. Asoutput PLL signal POUT is at H level at time t1, select signal SELswitches to L level and selector 77 selects input terminal A. As aresult, ring oscillator 79 has a longer delay time as not passingthrough delay line 75.

[0153] Thereafter, when output PLL signal goes to L level, select signalSEL switches to H level and selector 77 selects input terminal B. As aresult, ring oscillator 79 has a shorter delay time as not passingthrough delay line 75. Therefore, when selector control signal PSEL isat H level, as shown in FIG. 18, output PLL signal POUT has the H levelperiod longer than the L level period and has the duty ratio changedfrom 50%.

[0154] As described above, in PLL circuit 2 b of the second embodiment,the duty ratio of output PLL signal POUT can be adjusted by operatingselector control signal PSEL.

[0155] Although, the duty ratio of output PLL signal POUT has beendescribed above as being controlled by the activation/inactivation ofselector control signal PSEL, the duty ratio of output PLL signal POUTmay not always be controllable. A constant ratio between the H levelperiod and the L level period of output PLL signal POUT can always bekept by fixing selector control signal PSEL at H level. Here, the ratiobetween the H level period and the L level period of output PLL signalPOUT is stable because the activation/inactivation of selector controlsignal PSEL is not used.

[0156] In the case of digital PLL circuit such as PLL circuits 2 a, 2 bof the second embodiment as described above, the digital count valueoutput from the counter is basically determined by the ratio between thecycle of output PLL signal at that time and the gate delay of thetransistor included in the digital PLL circuit, namely, “the cycle ofoutput PLL signal/the gate delay”. The gate delay is affected by thecharacteristics of the transistor, which are also affected by variationsin manufacturing processes of the transistor, as well as temperatures,voltages, and the like.

[0157] Now consider that a circuit operated with output PLL signal froma digital PLL circuit is provided on the same substrate as the digitalPLL circuit. When “the cycle of output PLL signal/the gate delay” issmall, the circuit operated with the output PLL signal from the digitalPLL circuit has a small operational margin with respect to the outputPLL signal. It is therefore effective to change the duty ratio of theoutput PLL signal as necessary. When “the cycle of output PLL signal/thegate delay” is large, the circuit operated with the output PLL signalfrom the digital PLL circuit has a sufficient operational margin withrespect to the output PLL signal. It is thus not so effective if theduty ratio of the output PLL signal is changed. Therefore, the dutyratio of the output PLL signal may be 50%.

[0158] Furthermore, consider that the frequency of the output PLL signaloutput from the digital PLL circuit can be varied by software. When thefrequency of the output PLL signal is high, the circuit operated withthe output PLL signal from the digital PLL circuit has a smalloperational margin with respect to the output PLL signal. It istherefore effective to change the duty ratio of the output PLL signal asnecessary. When the frequency of the output PLL signal is low, thecircuit operated with the output PLL signal from the digital PLL circuithas a sufficient operational margin with respect to the output PLLsignal. It is thus not so effective if the duty ratio of the output PLLsignal is changed, and the duty ratio of the output PLL signal may be50%.

[0159] As described above, in accordance with the second embodiment,increased speed and reduced power consumption of the system includingclock generation circuit 1B can be realized by varying the duty ratio ofoutput PLL signal POUT output from PLL circuit 2B that is a component ofclock generation circuit 1B.

[0160] [Third Embodiment]

[0161]FIG. 19 is a circuit diagram showing a circuit configuration of aclock generation circuit 1C in accordance with a third embodiment of thepresent invention.

[0162] Clock generation circuit 1C of the third embodiment shown in FIG.19 includes a PLL circuit 2, a waveform generation circuit 81 a, and anAND gate 82.

[0163] PLL circuit 2 receives the input of reference clock signal CLK0and outputs output PLL signal POUT that is three times the frequency ofreference clock signal CLK0. It is noted that PLL circuit 2 may be ananalog PLL circuit, a digital PLL circuit, or any other PLL circuit, andthat three times is only an example, and basically, any multiplicationrate may be employed. Waveform generation circuit 81 a outputs a dutyratio control signal DTYa. AND gate 82 receives the inputs of output PLLsignal POUT and duty ratio control signal DTYa to output a clock signalCLKa.

[0164] Duty ratio control signal DTYa is a periodic signal having awaveform generated by waveform generation circuit 81 such that theperiod of time during which both output PLL signal POUT and duty ratiocontrol signal DTYa are at H level is different from that of the otherperiod of time.

[0165]FIG. 20 is an operational waveform diagram illustrating a circuitoperation of clock generation circuit 1C in accordance with the thirdembodiment of the present invention.

[0166] At time t1, in response to the rising of both of output PLLsignal POUT and duty ratio control signal DTYa, clock signal CLKa rises.At time t2, in response to the falling of output PLL signal POUT andduty ratio control signal DTYa, clock signal CLKa falls. Clock signalCLKa keeps falling until both output PLL signal POUT and duty ratiocontrol signal DTYa rise again at time t3.

[0167] Therefore, as shown in FIG. 20, clock signal CLKa has the H levelperiod longer than the L level period and has the duty ratio changedfrom 50%. When duty ratio control signal DTYa has the same frequency asreference clock signal CLK0, clock signal CLKa has the same frequency asreference clock signal CLK0. The duty ratio of clock signal CLKa can beadjusted by changing the frequency multiplication rate between referenceclock signal CLK0 and output PLL signal POUT from three times.

[0168]FIG. 21 is a circuit diagram showing a circuit configuration of aclock generation circuit 1D in accordance with the third embodiment ofthe present invention.

[0169] Clock generation circuit 1D of the third embodiment shown in FIG.21 includes a PLL circuit 2, a waveform generation circuit 81 d, and anOR gate 83.

[0170] PLL circuit 2 receives the input of reference clock signal CLK0and outputs output PLL signal POUT that is three times the frequency ofreference clock signal CLK0. It is noted that PLL circuit 2 may be ananalog PLL circuit, a digital PLL circuit, or any other PLL circuit, andthat three times is only an example, and basically, any multiplicationrate may be employed. Waveform generation circuit 81 b outputs a dutyratio control signal DTYb. OR gate 83 receives the inputs of output PLLsignal POUT and duty ratio control signal DTYb to output a clock signalCLKb.

[0171] Duty ratio control signal DTYb is a periodic signal having awaveform generated by waveform generation circuit 81 b such that theperiod of time during which output PLL signal POUT and duty ratiocontrol signal DTYb both are at L level is different from the otherperiod of time.

[0172]FIG. 22 is an operational waveform diagram illustrating a circuitoperation of clock generation circuit 1D in accordance with the thirdembodiment of the present invention.

[0173] At time t1, in response to the falling of both output PLL signalPOUT and duty ratio control signal DTYb, clock signal CLKb falls. Attime t2, in response to the rising of output PLL signal POUT, clocksignal CLKb rises. Thereafter, clock signal CLKb keeps rising until bothoutput PLL signal POUT and duty ratio control signal DTYb fall again attime t3.

[0174] Therefore, as shown in FIG. 22, clock signal CLKb has an H levelperiod longer than an L level period and has its duty ratio changed from50%. Furthermore, when duty ratio control signal DTYb has the samefrequency as reference clock signal CLK0, clock signal CLKb has the samefrequency as reference clock signal CLK0. The duty ratio of clock signalCLKb can be adjusted by changing the frequency multiplication ratebetween reference clock signal CLK0 and output PLL signal POUT fromthree times.

[0175] As described above, in accordance with the third embodiment,increased speed and reduced power of the system including the clockgeneration circuit can be realized by using the waveform generationcircuit to change the duty ratio of the clock signal output from theclock generation circuit.

[0176] [Fourth Embodiment]

[0177] Exemplary configurations of a system including at least one ofclock generation circuits 1A-1D of the first to third embodiments willnow be described.

[0178]FIG. 23 is a block diagram showing a configuration of a system 100in accordance with a fourth embodiment of the present invention.

[0179] System 100 of the fourth embodiment shown in FIG. 23 includes aclock generation circuit 1, a clock control register 101, a peripheralcircuit 102, a CPU (Central Processing Unit) 103, and a CPU bus 104.

[0180] Clock generation circuit 1 is any of clock generation circuits1A-1D of the first to third embodiments of the present invention, whichreceives reference clock signal CLK0 to output clock signal CLK toperipheral circuit 102 and CPU 103. Clock generation circuit 1 iscontrolled by an instruction from CPU 103. The duty ratio of clocksignal CLK and the on/off of the duty ratio control can be controlled byone or more control signals output from clock control register 101.

[0181] Here, the control signal refers to driving capability controlsignals DRVP, DRVN in buffer circuit 10 b of the first embodiment,timing control signals TMGP, TMGN in buffer circuit 10 d of the firstembodiment, delay control signal DLY in buffer circuits 10 f, 10 g ofthe first embodiment, count value control signal PCNT in PLL circuit 2Aof the second embodiment, selector control signal PSEL in PLL circuit 2Aof the second embodiment, duty ratio control signals DTYa, DTYb in clockgeneration circuits 1C, 1D of the third embodiment, or the like.

[0182] Clock control register 101 can perform reading/writing of aregister value from/to CPU 103 through CPU bus 104. Therefore, theregister value held in clock control register 101 is mapped to anaddress space in CPU 103.

[0183] Peripheral circuit 102 can be controlled by CPU 103 through CPUbus 104 and communicate signals with clock generation circuit 1 and dockcontrol register 101. Peripheral circuit 102 may be a circuit assistingin the operation of system 100, a circuit receiving clock signal CLK forits operation, or a circuit such as a current measuring circuit or atemperature measuring circuit.

[0184] When peripheral circuit 102 is a current measuring circuit, anamount of current in a circuit operated with clock signal CLK ismeasured with the duty ratio of clock signal CLK gradually varied, andthe duty ratio at which the amount of current is minimum is determinedas the duty ratio of clock signal CLK, so that an optimum duty ratio ofclock signal CLK can be set.

[0185] When peripheral circuit 102 is a temperature measuring circuit, atemperature of a circuit operated with clock signal CLK is measured withthe duty ratio of clock signal CLK gradually varied, and the duty ratioat which the temperature is lowest is determined as the duty ratio ofclock signal CLK, so that an optimum duty ratio of dock signal CLK canbe set.

[0186] CPU 103 controls the entire system 100 by controlling clockgeneration circuit 1, clock control register 101, and peripheral circuit102 directly or through CPU bus 104. In this manner, in system 100 ofthe fourth embodiment, the duty ratio of clock signal CLK can becontrolled by software.

[0187]FIG. 24 is a block diagram showing a configuration of a system 200in accordance with the fourth embodiment of the present invention.

[0188] System 200 of the fourth embodiment shown in FIG. 24 differs fromsystem 100 in that clock control register 101 is replaced with a clockcontrol circuit 201. Therefore, the description of the same componentsas system 100 will not be repeated here.

[0189] Clock control circuit 201 is a dedicated control circuitcontrolling clock generation circuit 1 and is controlled by CPU 103through CPU bus 104. The control of the duty ratio of dock signal CLK orthe on/off of the duty ratio control is performed by one or more controlsignals output from clock control circuit 201.

[0190] Here, the control signal refers, for example, to drivingcapability control signals DRVP, DRVN, timing control signals TMGP,TMGN, delay control signal DLY, count value control signal PCNT,selector control signal PSEL, duty ratio control signals DTYa, DTYb, orthe like, as in system 100.

[0191] In this manner, in system 200 of the fourth embodiment, the dutyratio of clock signal CLK can be controlled by software.

[0192] In systems 100, 200 of the fourth embodiment, CPU 103 is operatedwith clock signal CLK from clock generation circuit 1 that is indirectlycontrolled by CPU 103. Such a system configuration, however, is onlyshown by way of example, and CPU 103 may be operated with a clock signalfrom another clock generation circuit.

[0193]FIG. 25 is a block diagram showing a configuration of a system 300in accordance with the fourth embodiment of the present invention.

[0194] System 300 of the fourth embodiment shown in FIG. 25 includesclock generation circuit 1 and an external terminal 301.

[0195] Clock generation circuit 1 is any of clock generation circuits1A-1D of the first to third embodiments of the present invention, whichreceives reference clock signal CLK0 to output clock signal CLK. System300 can perform the control of duty ratio of clock signal CLK or theon/off of the duty ratio control using one or more control signalsdirectly input from external terminal, or one or more control signalsgenerated through an operation on the input from external terminal 301.

[0196] Here, as in system 100, the control signal refers, for example,to driving capability control signals DRVP, DRVN, timing control signalsTMGP, TMGN, delay control signal DLY, a count value control signal PCNT,selector control signal PSEL, duty ratio control signals DTYa, DTYb, orthe like.

[0197] An external ammeter may be connected to external terminal 301 tomeasure a power consumption of a circuit operated with clock signal CLKwith the duty ratio of clock signal varied gradually, and the duty ratioat which the power consumption is minimum is employed as the duty ratioof clock signal CLK, so that an optimum duty ratio of clock signal CLKcan be set.

[0198] Alternatively, an external thermometer may be connected toexternal terminal 301 to measure a temperature of a circuit operatedwith clock signal CLK with the duty ratio of clock signal CLK variedgradually, and the duty ratio at which the temperature is lowest isdetermined as the duty ratio of clock signal CLK, so that an optimumduty ratio of clock signal CLK can be set.

[0199] In this manner, in system 300 of the fourth embodiment, the dutyratio of clock signal CLK can be determined, for example, depending onthe system in use, by controlling clock generation circuit 1 with theinput from external terminal 301. In addition, the duty ratio of clocksignal CLK can be controlled by an external different system or controlcircuit.

[0200]FIG. 26 is a block diagram showing a configuration of a system 400in accordance with the fourth embodiment of the present invention.

[0201] System 400 of the fourth embodiment shown in FIG. 26 includesclock generation circuit 1 and a fuse circuit 401.

[0202] Clock generation circuit 1 is any of clock generation circuits1A-1D of the first to third embodiments of the present invention, whichreceives reference clock signal CLK0 to output clock signal CLK. System400 can control the duty ratio of clock signal CLK or the on/off of theduty ratio control using one or more control signals from fuse circuit401. Fuse circuit 401 sets the control signal, for example, using atechnique such as laser trimming.

[0203] Here, as in system 100, the control signal refers, for example,to driving capability control signals DRVP, DRVN, timing control signalsTMGP, TMGN, delay control signal DLY, count value control signal PCNT,selector control signal PSEL, duty ratio control signals DTYa, DTYb, orthe like.

[0204] In this manner, clock generation circuit 1 is controlled by fusecircuit 401. Therefore, where system 400 is incorporated into an LSI,for example, the characteristics of LSI is evaluated in a manufacturingtest and the duty ratio of clock signal CLK can be determined based onthe test result.

[0205]FIG. 27 is a block diagram showing a configuration of a system 500in accordance with the fourth embodiment of the present invention.

[0206] System 500 of the fourth embodiment shown in FIG. 27 includesclock generation circuit 1 and an ROM (Read Only Memory) circuit 501.

[0207] Clock generation circuit 1 is any of clock generation circuits1A-1D of the first to third embodiments of the present invention, whichreceives reference clock signal CLK0 to output clock signal CLK. System500 can control the duty ratio of clock signal CLK or the on/off of theduty ratio control using one or more control signals from ROM circuit501.

[0208] Here, as in system 100, the control signal refers, for example,to driving capability control signals DRVP, DRVN, timing control signalsTMGP, TMGN, delay control signal DLY, count value control signal PCNT,selector control signal PSEL, duty ratio control signals DTYa, DTYb, orthe like.

[0209] ROM circuit 401 may be, for example, a mask ROM, a PROM(Programmable ROM), an EPROM (Electrically Programmable ROM), or aEEPROM (Electrically Erasable and Programmable ROM) such as a flashmemory. An optimum duty ratio of clock signal CLK can thus be determineddepending on the system in use, by controlling clock generation circuit1 by ROM circuit 501.

[0210]FIG. 28 is a block diagram showing a configuration of a system 600in accordance with the fourth embodiment of the present invention.

[0211] System 600 of the fourth embodiment shown in FIG. 28 includesclock generation circuit 1 and a timer circuit 601.

[0212] Clock generation circuit 1 is any of clock generation circuits1A-1D of the first to third embodiments, which receives reference clocksignal CLK0 to output clock signal CLK. System 600 can control the dutyratio of clock signal CLK or the on/off of the duty ratio control usingone or more control signals form timer circuit 601.

[0213] Here, as in system 100, the control signal refers, for example,to driving capability control signals DRVP, DRVN, timing control signalsTMGP, TMGN, delay control signal DLY, count value control signal PCNT,selector control signal PSEL, duty ratio control signals DTYa, DTYb, orthe like.

[0214] Timer circuit 601 may be dedicated to clock generation circuit 1.Alternatively, where system 600 is integrated with a system LSI, it maybe shared with a peripheral circuit or may be at a CPU in the system LSIto measure the number of cycles.

[0215] In this manner, clock generation circuit 1 is controlled by timercircuit 601 to allow the duty ratio of clock signal CLK to be variedevery certain times or every certain cycles, so that the duty ratio ofclock signal CLK can be controlled.

[0216] As an example of the system in the fourth embodiment of thepresent invention, systems 100-600 shown in FIGS. 23-28 may be combined.Referring to FIG. 23, assume that peripheral circuit 102 is a compositecircuit including external terminal 301 of system 300, fuse circuit 401of system 400, ROM circuit 501 of system 500, timer 601 of system 600,and a circuit receiving clock signal CLK to operate.

[0217] In this case, the duty ratio of clock signal CLK can be setindividually for clock control register 101, external terminal 301, fusecircuit 401, ROM circuit 501, and timer circuit 601. During theoperation of the circuit receiving clock signal CLK for operation, theduty ratio of clock signal CLK can be finely adjusted for each of clockcontrol register 101, external terminal 301, fuse circuit 401, ROMcircuit 501, and timer circuit 601, from CPU 103. It is noted that clockcontrol register 101 may be replaced with clock control circuit 201 ofsystem 200.

[0218] As another example of the system in the fourth embodiment of thepresent invention, systems 100-600 shown in FIGS. 23-28 may beselectively used depending on the modules included in LSI. Referring toFIG. 23, assume that peripheral circuit 102 is a composite circuitincluding external terminal 301 of system 300, fuse circuit 401 ofsystem 400, ROM circuit 501 of system 500, timer circuit 601 of system600, and a circuit divided into a plurality of modules receiving clockCLK for operation.

[0219] In this case, depending on each module of the circuit receivingclock signal CLK for operation, clock control register 101, externalterminal 301, fuse circuit 401, ROM circuit 501, and timer circuit 601is selected as appropriate, so that an optimum duty ratio of clocksignal CLK can be set for each module. As a result, a more optimumsystem can be realized as a whole. It is noted that clock controlregister 101 may be replaced with clock control circuit 201 of system200.

[0220] Referring to FIG. 23, when peripheral circuit 102 includes acircuit divided into a plurality of modules receiving clock signal CLKfor operation, an optimum duty ratio of clock signal CLK can bedetermined and changed for a plurality of modules as a whole, or may bedetermined and changed for each module.

[0221] If an optimum duty ratio of clock signal CLK is measured andchanged for the modules as a whole, only a single circuit is required asa measurement circuit, a duty ratio changing circuit, and the like,thereby simplifying the circuit structure. If an optimum duty ratio ofclock signal is determined and changed for each module, a respectivecircuit is required as a measurement circuit, a duty ratio changingcircuit, and the like, thereby complicating the circuit structure,although the optimum duty ratio of clock signal CLK can be determinedand changed more flexibly.

[0222] Next, referring to FIG. 23, assume that peripheral circuit 102includes a circuit divided into a plurality of modules receiving clocksignal CLK for operation and that clock signal CLK output from clockgeneration circuit 1 is supplied not only to the inside but also to theoutside of system 100.

[0223] In this case, it is possible, for example, to set the duty ratioof clock signal CLK to be supplied to the outside of system 100 at 50%and to set only the duty ratio of clock signal CLK to be supplied toeach module inside system 100, individually. Because of such duty ratiosetting, it is possible to avoid the risk of malfunction of a particularmodule inside system 100 due to the difference in duty ratio of clocksignal CLK. It is also possible to avoid the risk of reducingperformance of a particular module inside system 100 due to thedifference in duty ratio of clock signal CLK.

[0224] In addition, because of the duty ratio setting as describedabove, the duty ratio is properly shifted from system 100 to another LSIon the system, resulting in the shifted operation timings between them.Therefore, the timings of current peak are shifted from each other,thereby reducing the possibility of the malfunction of system 100 due toovercurrent, and reducing the noise due to EMI and the like.

[0225] As described above, in accordance with the fourth embodiment, theperformance of the system can be improved by constructing the systemincluding clock generation circuits 1A-1D of the first to thirdembodiments of the present invention.

[0226] Although the present invention has been described and illustratedin detail, it is clearly understood that the same is by way ofillustration and example only and is not to be taken by way oflimitation, the spirit and scope of the present invention being limitedonly by the terms of the appended claims.

What is claimed is:
 1. A clock generation circuit comprising: afrequency-multiplying circuit receiving an input of a reference clocksignal and outputting a same or frequency-multiplied clock signal ofsaid reference clock signal; and a buffering portion buffering saidclock signal, wherein said buffering portion includes at least onebuffer circuit buffering said clock signal such that a logic low periodand a logic high period of said clock signal are different from eachother.
 2. The clock generation circuit according to claim 1 wherein saidbuffer circuit includes a first inverter circuit receiving said clocksignal and a second inverter circuit receiving an output of saidinverter circuit, one of said first and second inverter circuitsincluding a first transistor connected between a power supply node andan output node and having one polarity and a second transistor connectedbetween said output node and a ground node and having the otherpolarity, and a gate delay amount for an input signal at said firsttransistor and a gate delay amount for an input signal at said secondtransistor are different from each other.
 3. The clock generationcircuit according to claim 1 wherein at least one of a power supplypotential or a ground potential in said buffer circuit is different fromanother power supply voltage or ground voltage in said bufferingportion.
 4. The clock generation circuit according to claim 1 wherein asubstrate potential of a transistor included in said buffer circuit isdifferent from a substrate potential of another transistor included insaid buffering portion.
 5. A clock generation circuit comprising: afrequency-multiplying circuit receiving an input of a reference clocksignal and outputting a same or frequency-multiplied clock signal ofsaid reference clock signal, said clock signal having a logic highperiod and a logic low period different from each other; and a bufferingportion buffering said clock signal.
 6. The clock generation circuitaccording to claim 5 wherein said frequency-multiplied circuit includesa ring oscillator, a comparator comparing a phase of said clock signaloutput from said ring oscillator with a phase of said reference clocksignal, a counter determining a digital count value based on a phasecomparison result output from said comparator, and a control circuitincrementing/decrementing said digital count value in response to arising/falling of said clock signal, said ring oscillator including adelay line varying a delay time in accordance with said digital countvalue.
 7. The clock generation circuit according to claim 5 wherein saidfrequency-multiplying circuit includes a ring oscillator, a comparatorcomparing a phase of said clock signal output from said ring oscillatorwith a phase of said reference clock signal, and a counter determining adigital count value based on a phase comparison result output from saidcomparator, said ring oscillator including first and second delay linesconnected in series for receiving said digital count value fordetermining a delay time, and a selector selecting and outputting aninput from one of said first and second delay lines in accordance withsaid clock signal.
 8. A clock generation circuit comprising: afrequency-multiplying circuit receiving an input of a reference clocksignal and outputting a same or frequency-multiplied clock signal ofsaid reference clock signal; a waveform generation circuit outputting aduty ratio control signal; and an AND gate receiving said clock signaland said duty ratio control signal, wherein in said duty ratio controlsignal, a period of time during which both of said clock signal and saidduty ratio control signal are logic high is different from the otherperiod of time.
 9. A clock generation circuit comprising: afrequency-multiplying circuit receiving an input of a reference clocksignal and outputting a same or frequency-multiplied clock signal ofsaid reference clock signal; a waveform generation circuit outputting aduty ratio control signal; and an OR gate receiving said clock signaland said duty ratio control signal, wherein in said duty ratio controlsignal, a period of time during which both of said clock signal and saidduty ratio control signal are logic low is different from the otherperiod of time.
 10. A clock generation circuit comprising: afrequency-multiplying circuit receiving an input of a reference clocksignal and outputting a same or frequency-multiplied clock signal ofsaid reference clock signal; and a buffering portion buffering saidclock signal, wherein said buffering portion includes at least onebuffer circuit capable of changing a duty ratio of said clock signal.11. The clock generation circuit according to claim 10 wherein saidbuffer circuit includes a first inverter circuit receiving said clocksignal, and a second inverter circuit receiving an output of said firstinverter circuit, one of said first and second inverter circuitsincluding a plurality of first transistors connected in parallel betweena power supply node and an output node and having one polarity, aplurality of second transistors connected in parallel between saidoutput node and a ground node and having the other polarity, and adriving capability control portion controlling on/off of said pluralityof first and second transistors respectively using a plurality ofdriving capability control signals.
 12. The clock generation circuitaccording to claim 10 wherein said buffer circuit includes a firstinverter circuit receiving said clock signal, a second inverter circuitreceiving an output of said first inverter circuit, and a timing controlportion controlling rising or falling timing of a signal level outputfrom said first inverter circuit to said second inverter circuit using aplurality of timing control signals.
 13. The clock generation circuitaccording to claim 10 wherein at least one of a power supply potentialand a ground potential of said buffer circuit can be varied using acontrol signal.
 14. The clock generation circuit according to claim 10wherein a substrate potential of a transistor included in said buffercircuit can be varied using a control signal.
 15. The clock generationcircuit according to claim 10 further comprising: a delay circuitcapable of controlling a delay time using a delay control signal; and alogic element receiving an output signal from said delay circuit and thereference clock signal for outputting a clock signal.
 16. The clockgeneration circuit according to claim 15 wherein said logic element isan AND gate.
 17. The clock generation circuit according to claim 15wherein said logic element is an OR gate.
 18. A clock generation circuitcomprising: a frequency-multiplying circuit receiving an input of areference clock signal and outputting a same or frequency-multipliedclock signal of said reference clock signal; and a buffering portionbuffering said clock signal, wherein said frequency-multiplying circuitcan change a duty ratio of said clock signal.
 19. The clock generationcircuit according to claim 18 wherein said frequency-multiplying circuitincludes a ring oscillator, a comparator comparing a phase of said clocksignal output from said ring oscillator with a phase of said referenceclock signal, a counter determining a digital count value based on aphase comparison result output from said comparator, and a controlcircuit incrementing/decrementing said digital count value in accordancewith a rising/falling of said clock signal when a count value controlsignal has a prescribed value, said ring oscillator including a delayline varying a delay time in accordance with said digital count value.20. The clock generation circuit according to claim 19 wherein whethersaid count value control signal takes said prescribed value isdetermined in accordance with said digital count value.
 21. The clockgeneration circuit according to claim 19 wherein whether said countvalue control signal takes said prescribed value is determined inaccordance with a frequency of said clock signal.
 22. The clockgeneration circuit according to claim 18 wherein saidfrequency-multiplying circuit includes a ring oscillator, a comparatorcomparing a phase of said clock signal output from said ring oscillatorwith a phase of said reference clock signal, a counter determining adigital count value based on a phase comparison result output from saidcomparator, and a logic element receiving a selector control signal andsaid clock signal for outputting a select signal, said ring oscillatorincluding first and second delay lines connected in series for receivingsaid digital count value for determining a delay time, and a selectorselecting and outputting an input from one of said first and seconddelay lines in accordance with said select signal.
 23. The clockgeneration circuit according to claim 22 wherein whether said selectorcontrol signal takes said prescribed value is determined in accordancewith said digital count value.
 24. The clock generation circuitaccording to claim 22 wherein whether said selector control signal takessaid prescribed value is determined in accordance with a frequency ofsaid clock signal.
 25. A clock generation circuit comprising: afrequency-multiplying circuit receiving an input of a reference clocksignal and outputting a same or frequency-multiplied clock signal ofsaid reference clock signal; a waveform generation circuit generating aduty ratio control signal; and an AND gate receiving said clock signaland said duty ratio control signal, wherein in said duty ratio controlsignal, a ratio between a period of time during which both of said clocksignal and said duty ratio control signal are logic high and the otherperiod of time can be varied.
 26. A clock generation circuit comprising:a frequency-multiplying circuit receiving an input of a reference clocksignal and outputting a same or frequency-multiplied clock signal ofsaid reference clock signal; a waveform generation circuit generating aduty ratio control signal; and an OR gate receiving said clock signaland said duty ratio control signal, wherein in said duty ratio controlsignal, a ratio between a period of time during which both of said clocksignal and said duty ratio control signal are logic low and the otherperiod of time can be varied.
 27. The clock generation circuit accordingto claim 10 further comprising an external terminal, wherein a dutyratio of said clock signal or on/off of duty ratio control is controlledby a signal from said external terminal.
 28. The clock generationcircuit according to claim 18 further comprising an external terminal,wherein a duty ratio of said clock signal or on/off of duty ratiocontrol is controlled by a signal from said external terminal.
 29. Theclock generation circuit according to claim 25 further comprising anexternal terminal, wherein a duty ratio of said clock signal or on/offof duty ratio control is controlled by a signal from said externalterminal.
 30. The clock generation circuit according to claim 26 furthercomprising an external terminal, wherein a duty ratio of said clocksignal or on/off of duty ratio control is controlled by a signal fromsaid external terminal.
 31. The clock generation circuit according toclaim 10 wherein a duty ratio of said clock signal or on/off of dutyratio control is controlled based on an operating current of a circuitreceiving said clock signal.
 32. The clock generation circuit accordingto claim 18 wherein a duty ratio of said clock signal or on/off of dutyratio control is controlled based on an operating current of a circuitreceiving said clock signal.
 33. The clock generation circuit accordingto claim 25 wherein a duty ratio of said clock signal or on/off of dutyratio control is controlled based on an operating current of a circuitreceiving said clock signal.
 34. The clock generation circuit accordingto claim 26 wherein a duty ratio of said clock signal or on/off of dutyratio control is controlled based on an operating current of a circuitreceiving said clock signal.
 35. The clock generation circuit accordingto claim 10 wherein a duty ratio of said clock signal or on/off of dutyratio control is controlled based on a temperature of a circuitreceiving said clock signal.
 36. The clock generation circuit accordingto claim 18 wherein a duty ratio of said clock signal or on/off of dutyratio control is controlled based on a temperature of a circuitreceiving said clock signal.
 37. The clock generation circuit accordingto claim 25 wherein a duty ratio of said clock signal or on/off of dutyratio control is controlled based on a temperature of a circuitreceiving said clock signal.
 38. The clock generation circuit accordingto claim 26 wherein a duty ratio of said clock signal or on/off of dutyratio control is controlled based on a temperature of a circuitreceiving said clock signal.
 39. The clock generation circuit accordingto claim 10 further comprising a fuse circuit, wherein a duty ratio ofsaid clock signal or on/off of duty ratio control is controlled fromsaid fuse circuit.
 40. The clock generation circuit according to claim18 further comprising a fuse circuit, wherein a duty ratio of said clocksignal or on/off of duty ratio control is controlled from said fusecircuit.
 41. The clock generation circuit according to claim 25 furthercomprising a fuse circuit, wherein a duty ratio of said clock signal oron/off of duty ratio control is controlled from said fuse circuit. 42.The clock generation circuit according to claim 26 further comprising afuse circuit, wherein a duty ratio of said clock signal or on/off ofduty ratio control is controlled from said fuse circuit.
 43. The clockgeneration circuit according to claim 10 further comprising a read-onlycircuit, wherein a duty ratio of said clock signal or on/off of dutyratio control is controlled from said read-only circuit.
 44. The clockgeneration circuit according to claim 18 further comprising a read-onlycircuit, wherein a duty ratio of said clock signal or on/off of dutyratio control is controlled from said read-only circuit.
 45. The clockgeneration circuit according to claim 25 further comprising a read-onlycircuit, wherein a duty ratio of said clock signal or on/off of dutyratio control is controlled from said read-only circuit.
 46. The clockgeneration circuit according to claim 26 further comprising a read-onlycircuit, wherein a duty ratio of said clock signal or on/off of dutyratio control is controlled from said read-only circuit.
 47. The clockgeneration circuit according to claim 10 further comprising a timercircuit, wherein a duty ratio of said clock signal or on/off of dutyratio control is controlled from said timer circuit.
 48. The clockgeneration circuit according to claim 18 further comprising a timercircuit, wherein a duty ratio of said clock signal or on/off of dutyratio control is controlled from said timer circuit.
 49. The clockgeneration circuit according to claim 25 further comprising a timercircuit, wherein a duty ratio of said clock signal or on/off of dutyratio control is controlled from said timer circuit.
 50. The clockgeneration circuit according to claim 26 further comprising a timercircuit, wherein a duty ratio of said clock signal or on/off of dutyratio control is controlled from said timer circuit.
 51. A systemcomprising: a clock generation circuit outputting a clock signal; aclock controlling circuit controlling a duty ratio of said clock signalusing a control signal; and a central processing unit controlling saidclock controlling circuit, said clock generation circuit including afrequency-multiplying circuit receiving an input of a reference clocksignal and outputting said clock signal same as or multiplied infrequency of said reference clock signal, and a buffering portionbuffering said clock signal, wherein said buffering portion includes atleast one buffer circuit capable of changing a duty ratio of said clocksignal.
 52. A system comprising: a clock generation circuit outputting aclock signal; a clock controlling circuit controlling a duty ratio ofsaid clock signal using a control signal; and a central processing unitcontrolling said clock controlling circuit, said clock generationcircuit including a frequency-multiplying circuit receiving an input ofa reference clock signal and outputting said clock signal same as ormultiplied in frequency of said reference clock signal, and a bufferingportion buffering said clock signal, wherein said frequency-multiplyingcircuit can change a duty ratio of said clock signal.
 53. A systemcomprising: a clock generation circuit outputting a clock signal; aclock controlling circuit controlling a duty ratio of said clock signalusing a control signal; and a central processing unit controlling saidclock controlling circuit, said clock generation circuit including afrequency-multiplying circuit receiving an input of a reference clocksignal and outputting said clock signal same as or multiplied infrequency of said reference clock signal, a waveform generation circuitgenerating a duty ratio control signal, and an AND gate receiving saidclock signal and said duty ratio control signal, wherein in said dutyratio control signal, a ration between a period of time during whichboth of said clock signal and said duty ratio control signal are logichigh and the other period of time can be varied.
 54. A systemcomprising: a clock generation circuit outputting a clock signal; aclock controlling circuit controlling a duty ratio of said clock signalusing a control signal; and a central processing unit controlling saidclock controlling circuit, said clock generation circuit including afrequency-multiplying circuit receiving an input of a reference clocksignal and outputting said clock signal same as or multiplied infrequency of said reference clock signal, a waveform generation circuitgenerating a duty ratio control signal, and an OR gate receiving saidclock signal and said duty ratio control signal, wherein in said dutyratio control signal, a ratio between a period of time during which bothof said clock signal and said duty ratio control signal are logic lowand the other period of time can be varied.
 55. The system according toclaim 51 further comprising a current measurement circuit measuring anoperating current of a circuit receiving said clock signal, wherein saidcentral processing unit controls a duty ratio of said clock signal oron/off of duty ratio control based on a measurement result of saidoperating current.
 56. The system according to claim 52 furthercomprising a current measurement circuit measuring an operating currentof a circuit receiving said clock signal, wherein said centralprocessing unit controls a duty ratio of said clock signal or on/off ofduty ratio control based on a measurement result of said operatingcurrent.
 57. The system according to claim 53 further comprising acurrent measurement circuit measuring an operating current of a circuitreceiving said clock signal, wherein said central processing unitcontrols a duty ratio of said clock signal or on/off of duty ratiocontrol based on a measurement result of said operating current.
 58. Thesystem according to claim 54 further comprising a current measurementcircuit measuring an operating current of a circuit receiving said clocksignal, wherein said central processing unit controls a duty ratio ofsaid clock signal or on/off of duty ratio control based on a measurementresult of said operating current.
 59. The system according to claim 51further comprising a temperature measurement circuit measuring atemperature of a circuit receiving said clock signal, wherein saidcentral processing unit controls a duty ratio of said clock signal oron/off of duty ratio control based on a measurement result of saidtemperature.
 60. The system according to claim 52 further comprising atemperature measurement circuit measuring a temperature of a circuitreceiving said clock signal, wherein said central processing unitcontrols a duty ratio of said clock signal or on/off of duty ratiocontrol based on a measurement result of said temperature.
 61. Thesystem according to claim 53 further comprising a temperaturemeasurement circuit measuring a temperature of a circuit receiving saidclock signal, wherein said central processing unit controls a duty ratioof said clock signal or on/off of duty ratio control based on ameasurement result of said temperature.
 62. The system according toclaim 54 further comprising a temperature measurement circuit measuringa temperature of a circuit receiving said clock signal, wherein saidcentral processing unit controls a duty ratio of said clock signal oron/off of duty ratio control based on a measurement result of saidtemperature.
 63. The system according to claim 51 further comprising atleast two of an external terminal, a fuse circuit, a read-only circuit,and a timer circuit, wherein said at least two circuits can individuallycontrol a duty ratio of said clock signal or on/off of duty ratiocontrol by an instruction from said central processing unit.
 64. Thesystem according to claim 52 further comprising at least two of anexternal terminal, a fuse circuit, a read-only circuit, and a timercircuit, wherein said at least two circuits can individually control aduty ratio of said clock signal or on/off of duty ratio control by aninstruction from said central processing unit.
 65. The system accordingto claim 53 further comprising at least two of an external terminal, afuse circuit, a read-only circuit, and a timer circuit, wherein said atleast two circuits can individually control a duty ratio of said clocksignal or on/off of duty ratio control by an instruction from saidcentral processing unit.
 66. The system according to claim 54 furthercomprising at least two of an external terminal, a fuse circuit, aread-only circuit, and a timer circuit, wherein said at least twocircuits can individually control a duty ratio of said clock signal oron/off of duty ratio control by an instruction from said centralprocessing unit.
 67. The system according to claim 51 furthercomprising: a plurality of module circuits receiving said clock signalfor operation; and at least two of an external terminal, a fuse circuit,a read-only circuit, and a timer circuit, wherein said at least twocircuits can control a duty ratio of said clock signal or on/off of dutyratio control for each of said plurality of module circuits by aninstruction from said central processing unit.
 68. The system accordingto claim 52 further comprising: a plurality of module circuits receivingsaid clock signal for operation; and at least two of an externalterminal, a fuse circuit, a read-only circuit, and a timer circuit,wherein said at least two circuits can control a duty ratio of saidclock signal or on/off of duty ratio control for each of said pluralityof module circuits by an instruction from said central processing unit.69. The system according to claim 53 further comprising: a plurality ofmodule circuits receiving said clock signal for operation; and at leasttwo of an external terminal, a fuse circuit, a read-only circuit, and atimer circuit, wherein said at least two circuits can control a dutyratio of said clock signal or on/off of duty ratio control for each ofsaid plurality of module circuits by an instruction from said centralprocessing unit.
 70. The system according to claim 54 furthercomprising: a plurality of module circuits receiving said clock signalfor operation; and at least two of an external terminal, a fuse circuit,a read-only circuit, and a timer circuit, wherein said at least twocircuits can control a duty ratio of said clock signal or on/off of dutyratio control for each of said plurality of module circuits by aninstruction from said central processing unit.
 71. The system accordingto claim 51 further comprising a plurality of module circuits receivingsaid clock signal for operation, wherein a duty ratio of said clocksignal can be controlled individually for each of said plurality ofmodule circuits by an instruction from said central processing unit. 72.The system according to claim 52 further comprising a plurality ofmodule circuits receiving said clock signal for operation, wherein aduty ratio of said clock signal can be controlled individually for eachof said plurality of module circuits by an instruction from said centralprocessing unit.
 73. The system according to claim 53 further comprisinga plurality of module circuits receiving said clock signal foroperation, wherein a duty ratio of said clock signal can be controlledindividually for each of said plurality of module circuits by aninstruction from said central processing unit.
 74. The system accordingto claim 54 further comprising a plurality of module circuits receivingsaid clock signal for operation, wherein a duty ratio of said clocksignal can be controlled individually for each of said plurality ofmodule circuits by an instruction from said central processing unit. 75.The system according to claim 51 further comprising a module circuitreceiving said clock signal for operation, wherein a duty ratio of saidclock signal can be set by an instruction from said central processingunit, individually for said clock signal being supplied to said modulecircuit and for said clock signal being supplied to a prescribedexternal circuit.
 76. The system according to claim 52 furthercomprising a module circuit receiving said clock signal for operation,wherein a duty ratio of said clock signal can be set by an instructionfrom said central processing unit, individually for said clock signalbeing supplied to said module circuit and for said clock signal beingsupplied to a prescribed external circuit.
 77. The system according toclaim 53 further comprising a module circuit receiving said clock signalfor operation, wherein a duty ratio of said clock signal can be set byan instruction from said central processing unit, individually for saidclock signal being supplied to said module circuit and for said clocksignal being supplied to a prescribed external circuit.
 78. The systemaccording to claim 54 further comprising a module circuit receiving saidclock signal for operation, wherein a duty ratio of said clock signalcan be set by an instruction from said central processing unit,individually for said clock signal being supplied to said module circuitand for said clock signal being supplied to a prescribed externalcircuit.